This application claims the benefit of Korean Patent Application Nos. 2005-07969, filed Jan. 28, 2005, and 2005-70859, filed Aug. 3, 2005, the disclosures of which are hereby incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a sub word line driver control signal generator and a control method thereof, to control a sub word line driver of a sub word line connected to a memory cell in a semiconductor memory device.
2. Description of the Related Art
In general, since a DRAM (Dynamic Random Access Memory) tends to have a large capacity, time taken to transfer a signal is more due to a wiring impedance delay than to a delay time of memory cell array itself. Thus, it has been necessary to match with a delay time by appropriately dividing a length of wire, so that a word line to select a row from a memory cell array is appropriately divided.
A word line is connected to a gate terminal of a transistor of a memory cell, and is generally formed of polysilicon. A specific resistance of polysilicon is considerably larger than that of metal. Further since a word line passes over a gate oxide of a cell transistor, capacitance is also very large. When resistance of a word line becomes large, an RC delay increases. A decoder output terminal for driving a word line should be large; thus, area consumption also increases, and much power is consumed in charging an overall word line to a high voltage and in discharging it. Thus, it is required to impedance match with a length of word line and reduce word line resistance.
To solve this problem a hierarchical word line driving method is used, in which a word line is divided into proper lengths to form sub word lines. Then the sub word lines are driven by a composition between a main word line of a row decoder and a sub word line of a sub word line driver.
A semiconductor memory device having such a hierarchical word line structure according to the prior art will be described, referring to FIGS. 1 to 3, as follows.
FIG. 1 is a block diagram and FIGS. 1A and 1B are circuit diagrams of regions thereof schematically illustrating a semiconductor memory device having a sub word line driver control signal generator (hereinafter, referred to as ‘SWD control signal generator’) according to the prior art. FIG. 2 is a circuit diagram illustrating in detail a connection between a sense amplifier region SAs 20 of FIG. 1 and the SWE control signal generator PXID_GEN. FIG. 3 is an equivalent circuit diagram of the SWD control signal generator PXID_GEN shown in FIG. 2.
Referring first to FIGS. 1, 1A and 1B, a semiconductor memory device according to the prior art includes a memory cell array MCA 14, a main word line decoder 12, a sense amplifier region 20, an SWD control signal generator region 18 and an SWD region containing SWDs 16.
In the memory cell array 14 (FIG. 1A), there are a plurality of memory cells MC and bit lines BL and BLB connected to the memory cells MC. Each memory cell MC is positioned at an intersection of a sub word line SWL and a bit line BL or BLB.
The main word line decoder 12 receives a specific address, e.g., RA2˜RA8, among inputted row addresses, then decodes it and supplies a boosted voltage VPP having a level higher than a power source voltage VDD to one main word line of a plurality of main word lines MWLs.
The sense amplifier region 20 (FIG. 1B) is positioned between memory cell arrays and has a plurality of sense amplifiers SAs to sense and amplify signals of bit lines BL and BLB.
The sub word line driver region 16 is positioned between memory cell arrays, and has a plurality of sub word line drivers SWDs driven by an SWD control signal PXID and an MWL signal.
The SWD control signal generator region 18 (FIG. 1B) is positioned between the sense amplifier regions, namely, at a conjunction region CONJ, and generates the SWD control signal PXID.
The SWD control signal generator PXID_GEN receives a sub word line decoding signal PXI generated by a sub word line decoder PXI_GEN 11, and applies the SWD control signal PXID to a corresponding sub word line driver SWD. The sub word line decoder PXI_GEN 11 receives specific row addresses, e.g., RA0 and RA1, and decodes them and generates a plurality of decoding signals PXI.
Referring to FIG. 2, there are a sense amplifier region 20 shown in more detail, a memory cell arrays 14a, 14b and an SWD control signal generator PXID_GEN and a plurality of sub word line drivers SWDs. Herewith, there is shown only one of two sub word line decoding signals PXI shown in FIG. 1, which is applied to the SWD control signal generator PXID_GEN.
In the sense amplifier region 20, a plurality of sense amplifiers SA and bit line isolation parts 24 and 26 are provided. The sense amplifiers SAs in the sense amplifier region 20 are electrically connected to one bit line pair BL, BLB among bit line pairs BL, BLB connected to memory cells (MC of FIG. 1) of adjacent memory cell arrays 14a, 14b, by using an isolation signal BISL or BISR, to sense and amplify a level of signal loaded on the connected bit line pair.
For example, when a sub word line SWL of a memory cell array 14b is activated, an isolation signal BISR becomes a high level and an isolation signal BISL becomes a low level. That is, transistors TR1, TR2, TR3 and TR4 of the bit line isolation part 24 positioned between a bit line pair BL, BLB of the memory cell array 14b and the plurality of sense amplifiers SAs are turned on. Thus, the bit line pair BL, BLB of the memory cell array 14b side is electrically connected to the sense amplifiers SAs. Meanwhile, transistors TR11, TR12, TR13 and TR14 of the bit line isolation part 26 positioned between a bit line pair BL, BLB of the memory cell array 14a and the plurality of sense amplifiers SAs are turned off. Thus, the connection between the bit line pair BL, BLB of the memory cell array 14a and the sense amplifier SA is cut off. Such a layout system, in which two adjacent memory cell arrays share one sense amplifier region, is called a shared sense amplifier system. This system is widely used with merits of reducing an area of sense amplifier, thus being applicable to a high integration.
With reference to FIG. 3, an SWD control signal generator PXID_GEN receives a sub word line decoding signal PXI and generates an SWD control signal PXID. When the sub word line decoding signal PXI has a high level, the SWD control signal PXID becomes a boosted voltage VPP by operation of inverters INV1, INV2 on the SWD control signal generator PXID_GEN. The inverters INV1 and INV2 are individually constructed of a pair of P-type MOS (Metal Oxide Semiconductor) transistor PM1, PM2 and N-type MOS transistor NM1, NM2. In other words, INV1 is constructed of PM1 and NM1, and INV2 is constructed of PM2 and NM2.
The SWD control signal PXID controls a plurality of sub word line drivers SWD provided in the sub word line driver region 16 (FIGS. 1A, 1B). For example, the sub word line driver is activated by a main word line MWL activated by a main word line decoder 12 and the activated SWD control signal PXID, to activate a sub word line SWL with a boosted voltage VPP having a level higher than a power source voltage VDD.
In such semiconductor memory device, for example, in the case that sub word lines corresponding to a memory cell array 14b are activated in FIG. 2, one sub word line of the sub word lines corresponding to the memory cell array 14b is activated in response to a signal applied to a main word line MWL and a sub word line decoding signal PXI so as to select a memory cell within the memory cell array 14b. In this case, it is unnecessary to apply an SWD control signal PXID to memory cell array 14a. 
However, the SWD control signal PXID of FIG. 2 enables the plurality of sub word line drivers SWD corresponding to the cell arrays 14a and 14b positioned on both sides of the sense amplifier SA.
In other words, a load of the SWD control signal generator PXID_GEN is very large, and this causes much power consumption in activating the SWD control signal PXID, and particularly, badly influences an operating characteristic of mobile equipment, etc. that require a low power consumption.